1. Field of the Invention
The present invention relates to semiconductor devices. More specifically, the present invention pertains to semiconductor devices which comprise closely spaced gate arrays having a plurality of unit semiconductor devices composed of gate-separated type insulated-gate field-effect transistors, the gates of which have an improved configuration.
2. Related Prior Art
Conventional semiconductor chip products of the channelless gate array type have an inner layout as shown in FIG. 15, in which a matrix of a plurality of gate-separated type unit semiconductor devices 2 is disposed on a silicon chip substrate 1 with a plurality of input/output buffer portions B along the peripheral area of the chip substrate so that they surround the matrix of unit devices. FIG. 16 illustrates a portion of the matrix to an enlarged scale. In this type of gate array, insulated-gate field-effect transistors in the same unit device are connected with each other and/or those belonging to different unit devices are connected by means of a first and/or second layers of aluminum wire deposited on the gate array, so that a desired large-scale logic circuitry can be obtained.
FIG. 17 is a circuit diagram of a unit device of the gate-separated type. The unit device 2 is comprised of two pairs of complementary insulated-gate field-effect transistors 2a and 2b of the gate-separated type (hereinafter referred to as "CMOSFET"). The gates G of the CMOSFETs are independent of one another, whereas FETs of the same conductivity type have a common drain D or source S.
FIG. 18 illustrates the physical layout of a conventional structure of the gate-separated unit device 2. As shown, an N-type substrate is provided with a rectangular-shaped P-type well region 3 which is formed by diffusing P-type impurities into the substrate. Polysilicon gates 4N, 5N are formed in the P-type well 3, over a gate oxide film, so that gates 4N, 5N extend across the P-type well and are symmetrical with each other. Adjacent to the P-type well 3 another pair of polysilicon gates 4P and 5P are formed. Gates 4P and 5P are offset from respective gates 4N and 5N in the channel width direction. A high impurity density diffused N-type region 6 is formed in a self-aligned manner by ion implantation of N-type impurities into P-type well 3 with utilization of the pair of polysilicon gates 4N and 5N. Likewise, a high impurity density diffused P-type region 7 is formed in a self-aligned manner by ion implantation of P-type impurities into the N-type substrate with utilization of the pair of polysilicon gates 4P and 5P. In addition, a heavily doped P-type stopper 8 is provided by diffusion adjacent to the region 6 in order to supply voltage V.sub.DD to the N-type substrate, and a heavily doped N-type stopper 9 is disposed adjacent to the region 7, the stopper 9 being used for supplying voltage V.sub.SS to P well 3.
Each of the polysilicon gates 4N, 5N, 4P and 5P has a U-shaped configuration comprising a long narrow gate electrode portion g and rectangular gate output terminal portions T.sub.1 and T.sub.2 extended from both ends of gate electrode portion g. Regions just below the respective gate electrode portions g function as channels. A portion of the heavily diffused N-type region 6 between the parallel disposed gate electrode portions g functions as a common drain or source region for the two N-channel MOSFETs. The common drain or source region for the two P-channel MOSFETs is likewise located between the parallel disposed gate electrode portions g in the heavily diffused P-type region 7.
In the gate array of the above-mentioned gate-separated unit device 2, as shown in FIG. 19, laterally adjacent CMOSFETs of the same unit device are wired between their gates oppositely arranged with each other so that the gate output terminal portions T.sub.1 and T.sub.2 thereof are connected via aluminum wires l.sub.1 (shown by solid lines) of a first layer through contact holes (denoted by "X" in the drawing), the first layer being laid on the gates, whereby the shortest wire-connection between adjacent CMOSFETs can be achieved. The diagonal wire connections between terminal portions T.sub.1 and T.sub.2 in the same unit device can be obtained as shown in FIG. 20, wherein one pair of diagonally positioned terminal portions T.sub.1 and T.sub.2 are connected by means of the aluminum wire l.sub.11 of a first layer through contact holes. The other pair of diagonally positioned terminal portions T.sub.1 and T.sub.2 are connected by means of aluminum wires l.sub.12 and l.sub.13 of the first layer and the aluminum wire l.sub.2 (shown by double solid lines) of a second layer laid on the first layer, through contact holes and connecting portions denoted by "O". The separated-type unit device has the benefits that it can easily be modified to a common-gate type unit device by wiring as shown in FIG. 19 or that it can be provided with the diagonal wiring as shown in FIG. 20, which is not applicable to the common-gate type unit device. Especially, the applicability of the diagonal wiring is useful to create functional devices such as transmission gates and the like.
However, the diagonal wiring requires a second or more layered aluminum wires if the wire length is intended to be as short as possible. If the second layered aluminum wires l.sub.2 are arranged for connection between the elements within the unit devices, the regions occupied by these second layered wires cannot be utilized to arrange other wires for connection between remotely positioned functional unit devices and between functional unit devices and the input/output buffers. Thus, those regions are called "wire prohibited tracks". Therefore, outer wiring feasibility (defined as ease of wiring among the remotely positioned functional unit devices and among the functional unit devices and the input/output buffers) becomes degraded as the number or area of the inner wires of the second or more layers increases.
For example, a D flip-flop shown in FIG. 21 can be constituted by two unit devices 2. In this case, "wire prohibited tracks" occur on the second layer of aluminum, as shown in FIG. 22, due to the diagonal wiring among the inner elements, so that the outer wiring feasibility becomes degraded.
It is of course possible that the two unit devices can be connected without using second layered aluminum wires. However, in this case, the respective aluminum wires of the first layer must be arranged so that they do not cross one another, which means that the total wire length becomes longer, so that the occupied regions for those long wires becomes larger. This degrades inner wiring feasibility (defined as ease of wiring among the elements in each of the unit devices and between adjacent unit devices). If the first layered wires become complicated and elongated, wire resistance and wire capacitance caused by the increased wired area will increase, and so wire time constant will become larger. This will cause a noticeable amount of delay in the device operation.